1. Field of the Invention
The present invention relates to techniques for improving the test quality of semiconductor chips at a low silicon area cost. More specifically, the present invention relates to a method and an apparatus that comprises a centralized on-chip built-in self-test (BIST) engine to test multiple on-chip memory structures.
2. Related Art
Recent advances in integrated circuit technology have largely been accomplished by decreasing the feature size of circuit elements on a semiconductor chip. This decreasing feature size makes it possible to incorporate increasingly more circuitry into a single semiconductor chip. This has enabled processor designers to incorporate multiple processor cores into a single microprocessor chip.
Unfortunately, as these microprocessor chips become increasingly more complicated, it is becoming harder to test all of the structures in a microprocessor chip. Logic circuitry and flip-flops within a microprocessor chip can be tested using scan techniques and automatic test pattern generation (ATPG). However, scan techniques cannot adequately test on-chip memory structures, such as cache memories or translation-lookaside buffers (TLBs).
For testing on-chip structures, a sequence of read and write operations in a specific addressing sequence is required to test for failure modes. Such control logic that generates this sequence and checks the results is typically designed to test memory structures. This control logic is referred to as “MBIST” engines in the literature. A BIST engine is a finite state machine, which is located in close proximity to a memory structure and is configured to perform successive read and write operations to the memory structure to test the memory structure. However, as more and more memory structures, such as TLBs and Branch History Tables (BHTs), are incorporated into microprocessor chips, it is becoming impractical to provide a separate BIST engine for each of these memory structures.
Hence, what is needed is a method and an apparatus for testing multiple on-chip memory structures without the area overhead of multiple BIST engines